`timescale 10ns / 1ps

module seg_i2c_top_tb ();

    reg                    clk;
    reg                    rst;
    wire        [5:0]      sel;
    wire        [7:0]      seg;
    wire                   scl;
    wire                   sda;

    initial begin
        $dumpfile("output/seg_i2c_top_tb.vcd");
        $dumpvars(0, seg_i2c_top_tb);
    end
  
    initial begin
        clk = 0;
        rst = 1;
        #10 rst = 0;
        #5_000_000 $stop;
    end

    always #1 clk = ~clk;
   
    seg_i2c_top seg_i2c_top_inst (
        .clk            (clk),
        .rst            (rst),
        .sel            (sel),
        .seg            (seg),
        .scl            (scl),
        .sda            (sda)
    );

endmodule  //seg_i2c_top_tb